External Hardware

All interfaces are documented in the core_top.v project template file. Check the HDL source for exact pin descriptions.

Physical RAM Available in User Cores

8Mx16 PSRAM

  • Latency: Very low
  • Bandwidth: Average to High

This type of pseudo-SRAM is a bit unique in that it can be accessed asynchronously with very low latency, but also be configured for 133mhz max speed synchronous bursts.

Each chip contains 2 separate dies with all signals wired in parallel except for the chip enables. Simple implementations can use the chip enable as an upper address bit.

Be careful to never assert both chip enable pins (CE0#, CE1#) to avoid bus contention.

128Kx16 SRAM

  • Latency: Very low
  • Bandwidth: Average

Standard asynchronous SRAM. Drive an address, strobe write enable or output enable. Latency is marginally faster than PSRAM but possible bandwidth is lower.

32Mx16 SDRAM

  • Latency: Average
  • Bandwidth: High

Standard synchronous DRAM. Comparable to PC133 SDRAM, except using a different voltage standard, its maximum frequency is increased to 166MHz. SDRAM is best accessed in bursts since every access requires activation and precharge overhead. DQM(H/L) are wired for byte-granular write masking.

Be mindful of the additional mode registers necessary to program during initialization. Consider referencing the industry-standard Micron 256M SDRAM datasheet for further details about how to use SDRAM.

Cartridge Bus + Link Port

Cores have complete access to the cartridge bus

  • Cartridge voltage is determined in hardware by a mechanical voltage selection switch (5v when the switch is depressed, 3.3v when not)
  • Cart power is enabled with the appropriate setting in core.json
  • Additional circuitry is present to prevent reset glitching. In 5v mode, pin30 is clamped low until a particular control pin is asserted. A core using pin30 should assert this pin (view the template HDL).
  • All pins are run through level translators and their direction can only be input or output. Most I/O pin directions are controlled in groups. For example, the data bus bits[7:0] are switched from input to output as one group. Some pins’ directions can be controlled independently (view the template HDL).
  • Link port power is voltage-controlled and power switched on the same rail as the cartridge bus.

Leave all cartridge pins in the default settings per the template HDL unless actively using the port. If the level translators are improperly configured while cartridge power is turned on, a user may lose data from an inserted cartridge.

Infrared Interface

Pocket contains an infrared transmitter LED and receiver circuit.

Transmit

Located in the same lightpipe as the power LED, the IR LED drive signal is active high. Because the LED is running near its maximum rated current, it should never be driven with DC. Only use PWM-type pulses to drive the LED at a duty cycle lower than 100%.

Receive

The receiver circuit has automatic gain control (AGC) to adjust for ambient light levels and expects to see typical PWM-type waveforms.

The receiver must be disabled whenever not in use as it consumes a nontrivial amount of power. Allow a few milliseconds for the AGC to stabilize when enabled.